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<center class="pagetitle">Group : router_stimulus_pkg::ral_reg_LOCK::cg_bits</center>
<div align="center"><a href="dashboard.html" ><b>dashboard</b></a> | hierarchy | modlist | <a href="groups.html" ><b>groups</b></a> | <a href="tests.html" ><b>tests</b></a> | asserts</div>

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<div>
<div class=modhdr>
<br clear=all>
<span class=titlename>Group : <a href="#"  onclick="showContent('router_stimulus_pkg::ral_reg_LOCK::cg_bits')">router_stimulus_pkg::ral_reg_LOCK::cg_bits</a></span>
<br clear=all>
<table align=left>
<tr class="sortablehead">
<td><b>SCORE</b></td><td>INSTANCES</td><td>WEIGHT</td><td>GOAL</td><td>AT LEAST</td><td>PER INSTANCE</td><td>AUTO BIN MAX</td><td>PRINT MISSING</td></tr><tr>
<td class="s2 cl rt"> 25.00</td>
<td class="s2 cl rt"> 25.00</td>
<td class="wht cl rt">1     </td>
<td class="wht cl rt">100   </td>
<td class="wht cl rt">1     </td>
<td class="wht cl rt">1     </td>
<td class="wht cl rt">64    </td>
<td class="wht cl rt">64    </td>
</tr></table><br clear=all>
<br clear=all>
<span class=repname>Source File(s) : </span>
<br clear=all>
<a href="javascript:void(0);"  onclick="openSrcFile('/home/shtp/ITP2025/Synopsys-ITP-Spring-2025-Design-Verification-main/Labs/UVM 1.2/labs/lab6/ral_host_regmodel.sv')">/home/shtp/ITP2025/Synopsys-ITP-Spring-2025-Design-Verification-main/Labs/UVM 1.2/labs/lab6/ral_host_regmodel.sv</a><br clear=all>
<br clear=all>
<span class=repname>1 Instances:</span>
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<table align=left>
<tr class="sortablehead">
<td class="alfsrt">NAME</td><td><b>SCORE</b></td><td>WEIGHT</td><td>GOAL</td><td>AT LEAST</td><td>AUTO BIN MAX</td><td>PRINT MISSING</td></tr><tr>
<td class="wht cl wordwrap"><a href="grp0.html#inst_tag_LOCK_bits"  onclick="showContent('LOCK_bits')">LOCK_bits</a></td>
<td class="s2 cl rt"> 25.00</td>
<td class="wht cl rt">1     </td>
<td class="wht cl rt">100   </td>
<td class="wht cl rt">1     </td>
<td class="wht cl rt">64    </td>
<td class="wht cl rt">64    </td>
</tr></table><br clear=all>
<br clear=all>
</div>
<hr>
<br clear=all>
<span class=repname>Summary for Group   router_stimulus_pkg::ral_reg_LOCK::cg_bits
</span>
<br clear=all>
<br clear=all>
<table align=left>
<tr class="sortablehead">
<td class="alfsrt">CATEGORY</td><td>EXPECTED</td><td>UNCOVERED</td><td>COVERED</td><td>PERCENT</td></tr><tr class="s2">
<td><a href="#var_tbl_router_stimulus_pkg::ral_reg_LOCK::cg_bits" >Variables</a></td>
<td class="rt">64</td>
<td class="rt">48</td>
<td class="rt">16</td>
<td class="rt">25.00 </td>
</tr></table><br clear=all>
<br clear=all>
<span class="repname" id="var_tbl_router_stimulus_pkg::ral_reg_LOCK::cg_bits">Variables for Group  router_stimulus_pkg::ral_reg_LOCK::cg_bits
</span>
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<table align=left>
<tr class="sortablehead">
<td class="alfsrt">VARIABLE</td><td>EXPECTED</td><td>UNCOVERED</td><td>COVERED</td><td>PERCENT</td><td>GOAL</td><td>WEIGHT</td><td>AT LEAST</td><td>AUTO BIN MAX</td><td>COMMENT</td></tr><tr class="s2">
<td><a href="#inst_tag_router_stimulus_pkg::ral_reg_LOCK::cg_bits.LOCK"  onclick="checkLink(this)" target="detailFrame">LOCK</a></td>
<td class="rt">64</td>
<td class="rt">48</td>
<td class="rt">16</td>
<td class="rt">25.00 </td>
<td class="rt">100</td>
<td class="rt">1</td>
<td class="rt">1</td>
<td class="rt">0</td>
<td></td>
</tr></table><br clear=all>
</div>
<div name='LOCK_bits'>
<a name="inst_tag_LOCK_bits"></a>
<hr>
<div class=modhdr>
<br clear=all>
<span class=titlename>Group Instance : <a href="groups.html#tag_LOCK_bits" >LOCK_bits</a></span>
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<table align=left>
<tr class="sortablehead">
<td><b>SCORE</b></td><td>WEIGHT</td><td>GOAL</td><td>AT LEAST</td><td>AUTO BIN MAX</td><td>PRINT MISSING</td></tr><tr>
<td class="s2 cl rt"> 25.00</td>
<td class="wht cl rt">1     </td>
<td class="wht cl rt">100   </td>
<td class="wht cl rt">1     </td>
<td class="wht cl rt">64    </td>
<td class="wht cl rt">64    </td>
</tr></table><br clear=all>
<br clear=all>
</div>
<hr>
<br clear=all>
<span class=repname>Summary for Group Instance   LOCK_bits
</span>
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<br clear=all>
<table align=left>
<tr class="sortablehead">
<td class="alfsrt">CATEGORY</td><td>EXPECTED</td><td>UNCOVERED</td><td>COVERED</td><td>PERCENT</td></tr><tr class="s2">
<td><a href="#var_tbl_LOCK_bits" >Variables</a></td>
<td class="rt">64</td>
<td class="rt">48</td>
<td class="rt">16</td>
<td class="rt">25.00 </td>
</tr></table><br clear=all>
<br clear=all>
<span class="repname" id="var_tbl_LOCK_bits">Variables for Group Instance  LOCK_bits
</span>
<br clear=all>
<table align=left>
<tr class="sortablehead">
<td class="alfsrt">VARIABLE</td><td>EXPECTED</td><td>UNCOVERED</td><td>COVERED</td><td>PERCENT</td><td>GOAL</td><td>WEIGHT</td><td>AT LEAST</td><td>AUTO BIN MAX</td><td>COMMENT</td></tr><tr class="s2">
<td><a href="#inst_tag_LOCK_bits.LOCK"  onclick="checkLink(this)" target="detailFrame">LOCK</a></td>
<td class="rt">64</td>
<td class="rt">48</td>
<td class="rt">16</td>
<td class="rt">25.00 </td>
<td class="rt">100</td>
<td class="rt">64</td>
<td class="rt">1</td>
<td class="rt">0</td>
<td></td>
</tr></table><br clear=all>
</div>
</div>
<div class="ui-layout-center">
<div class="ui-layout-center-inner-center">
<div name='router_stimulus_pkg::ral_reg_LOCK::cg_bits'>
<br clear=all>
<a name="inst_tag_router_stimulus_pkg::ral_reg_LOCK::cg_bits.LOCK"></a><span class="repname" id="inst_tag_router_stimulus_pkg::ral_reg_LOCK::cg_bits.LOCK">Summary for Variable LOCK</span>
<br clear=all>
<br clear=all>
<table align=left>
<tr class="sortablehead">
<td class="alfsrt">CATEGORY</td><td>EXPECTED</td><td>UNCOVERED</td><td>COVERED</td><td>PERCENT</td></tr><tr class="s2">
<td>User Defined Bins</td>
<td class="rt">64</td>
<td class="rt">48</td>
<td class="rt">16</td>
<td class="rt">25.00 </td>
</tr></table><br clear=all>
<br clear=all>
<span class=repname>User Defined Bins for LOCK</span>
<br clear=all>
<br clear=all>
<span class=repname>Uncovered bins</span>
<br clear=all>
<table align=left class="sortable">
<tr class="sortablehead">
<td class="alfsrt">NAME</td><td>COUNT</td><td>AT LEAST</td><td>NUMBER</td></tr><tr class="s3">
<td>bit_15_rd_as_1</td>
<td class="rt">0</td>
<td class="rt">1</td>
<td class="rt">1</td>
</tr><tr class="s3">
<td>bit_15_rd_as_0</td>
<td class="rt">0</td>
<td class="rt">1</td>
<td class="rt">1</td>
</tr><tr class="s3">
<td>bit_15_wr_as_0</td>
<td class="rt">0</td>
<td class="rt">1</td>
<td class="rt">1</td>
</tr><tr class="s3">
<td>bit_14_rd_as_1</td>
<td class="rt">0</td>
<td class="rt">1</td>
<td class="rt">1</td>
</tr><tr class="s3">
<td>bit_14_rd_as_0</td>
<td class="rt">0</td>
<td class="rt">1</td>
<td class="rt">1</td>
</tr><tr class="s3">
<td>bit_14_wr_as_0</td>
<td class="rt">0</td>
<td class="rt">1</td>
<td class="rt">1</td>
</tr><tr class="s3">
<td>bit_13_rd_as_1</td>
<td class="rt">0</td>
<td class="rt">1</td>
<td class="rt">1</td>
</tr><tr class="s3">
<td>bit_13_rd_as_0</td>
<td class="rt">0</td>
<td class="rt">1</td>
<td class="rt">1</td>
</tr><tr class="s3">
<td>bit_13_wr_as_0</td>
<td class="rt">0</td>
<td class="rt">1</td>
<td class="rt">1</td>
</tr><tr class="s3">
<td>bit_12_rd_as_1</td>
<td class="rt">0</td>
<td class="rt">1</td>
<td class="rt">1</td>
</tr><tr class="s3">
<td>bit_12_rd_as_0</td>
<td class="rt">0</td>
<td class="rt">1</td>
<td class="rt">1</td>
</tr><tr class="s3">
<td>bit_12_wr_as_0</td>
<td class="rt">0</td>
<td class="rt">1</td>
<td class="rt">1</td>
</tr><tr class="s3">
<td>bit_11_rd_as_1</td>
<td class="rt">0</td>
<td class="rt">1</td>
<td class="rt">1</td>
</tr><tr class="s3">
<td>bit_11_rd_as_0</td>
<td class="rt">0</td>
<td class="rt">1</td>
<td class="rt">1</td>
</tr><tr class="s3">
<td>bit_11_wr_as_0</td>
<td class="rt">0</td>
<td class="rt">1</td>
<td class="rt">1</td>
</tr><tr class="s3">
<td>bit_10_rd_as_1</td>
<td class="rt">0</td>
<td class="rt">1</td>
<td class="rt">1</td>
</tr><tr class="s3">
<td>bit_10_rd_as_0</td>
<td class="rt">0</td>
<td class="rt">1</td>
<td class="rt">1</td>
</tr><tr class="s3">
<td>bit_10_wr_as_0</td>
<td class="rt">0</td>
<td class="rt">1</td>
<td class="rt">1</td>
</tr><tr class="s3">
<td>bit_9_rd_as_1</td>
<td class="rt">0</td>
<td class="rt">1</td>
<td class="rt">1</td>
</tr><tr class="s3">
<td>bit_9_rd_as_0</td>
<td class="rt">0</td>
<td class="rt">1</td>
<td class="rt">1</td>
</tr><tr class="s3">
<td>bit_9_wr_as_0</td>
<td class="rt">0</td>
<td class="rt">1</td>
<td class="rt">1</td>
</tr><tr class="s3">
<td>bit_8_rd_as_1</td>
<td class="rt">0</td>
<td class="rt">1</td>
<td class="rt">1</td>
</tr><tr class="s3">
<td>bit_8_rd_as_0</td>
<td class="rt">0</td>
<td class="rt">1</td>
<td class="rt">1</td>
</tr><tr class="s3">
<td>bit_8_wr_as_0</td>
<td class="rt">0</td>
<td class="rt">1</td>
<td class="rt">1</td>
</tr><tr class="s3">
<td>bit_7_rd_as_1</td>
<td class="rt">0</td>
<td class="rt">1</td>
<td class="rt">1</td>
</tr><tr class="s3">
<td>bit_7_rd_as_0</td>
<td class="rt">0</td>
<td class="rt">1</td>
<td class="rt">1</td>
</tr><tr class="s3">
<td>bit_7_wr_as_0</td>
<td class="rt">0</td>
<td class="rt">1</td>
<td class="rt">1</td>
</tr><tr class="s3">
<td>bit_6_rd_as_1</td>
<td class="rt">0</td>
<td class="rt">1</td>
<td class="rt">1</td>
</tr><tr class="s3">
<td>bit_6_rd_as_0</td>
<td class="rt">0</td>
<td class="rt">1</td>
<td class="rt">1</td>
</tr><tr class="s3">
<td>bit_6_wr_as_0</td>
<td class="rt">0</td>
<td class="rt">1</td>
<td class="rt">1</td>
</tr><tr class="s3">
<td>bit_5_rd_as_1</td>
<td class="rt">0</td>
<td class="rt">1</td>
<td class="rt">1</td>
</tr><tr class="s3">
<td>bit_5_rd_as_0</td>
<td class="rt">0</td>
<td class="rt">1</td>
<td class="rt">1</td>
</tr><tr class="s3">
<td>bit_5_wr_as_0</td>
<td class="rt">0</td>
<td class="rt">1</td>
<td class="rt">1</td>
</tr><tr class="s3">
<td>bit_4_rd_as_1</td>
<td class="rt">0</td>
<td class="rt">1</td>
<td class="rt">1</td>
</tr><tr class="s3">
<td>bit_4_rd_as_0</td>
<td class="rt">0</td>
<td class="rt">1</td>
<td class="rt">1</td>
</tr><tr class="s3">
<td>bit_4_wr_as_0</td>
<td class="rt">0</td>
<td class="rt">1</td>
<td class="rt">1</td>
</tr><tr class="s3">
<td>bit_3_rd_as_1</td>
<td class="rt">0</td>
<td class="rt">1</td>
<td class="rt">1</td>
</tr><tr class="s3">
<td>bit_3_rd_as_0</td>
<td class="rt">0</td>
<td class="rt">1</td>
<td class="rt">1</td>
</tr><tr class="s3">
<td>bit_3_wr_as_0</td>
<td class="rt">0</td>
<td class="rt">1</td>
<td class="rt">1</td>
</tr><tr class="s3">
<td>bit_2_rd_as_1</td>
<td class="rt">0</td>
<td class="rt">1</td>
<td class="rt">1</td>
</tr><tr class="s3">
<td>bit_2_rd_as_0</td>
<td class="rt">0</td>
<td class="rt">1</td>
<td class="rt">1</td>
</tr><tr class="s3">
<td>bit_2_wr_as_0</td>
<td class="rt">0</td>
<td class="rt">1</td>
<td class="rt">1</td>
</tr><tr class="s3">
<td>bit_1_rd_as_1</td>
<td class="rt">0</td>
<td class="rt">1</td>
<td class="rt">1</td>
</tr><tr class="s3">
<td>bit_1_rd_as_0</td>
<td class="rt">0</td>
<td class="rt">1</td>
<td class="rt">1</td>
</tr><tr class="s3">
<td>bit_1_wr_as_0</td>
<td class="rt">0</td>
<td class="rt">1</td>
<td class="rt">1</td>
</tr><tr class="s3">
<td>bit_0_rd_as_1</td>
<td class="rt">0</td>
<td class="rt">1</td>
<td class="rt">1</td>
</tr><tr class="s3">
<td>bit_0_rd_as_0</td>
<td class="rt">0</td>
<td class="rt">1</td>
<td class="rt">1</td>
</tr><tr class="s3">
<td>bit_0_wr_as_0</td>
<td class="rt">0</td>
<td class="rt">1</td>
<td class="rt">1</td>
</tr></table><br clear=all>
<br clear=all>
<span class=repname>Covered bins</span>
<br clear=all>
<table align=left class="sortable">
<tr class="sortablehead">
<td class="alfsrt">NAME</td><td>COUNT</td><td>AT LEAST</td></tr><tr class="s10">
<td>bit_15_wr_as_1</td>
<td class="rt">1</td>
<td class="rt">1</td>
</tr><tr class="s10">
<td>bit_14_wr_as_1</td>
<td class="rt">1</td>
<td class="rt">1</td>
</tr><tr class="s10">
<td>bit_13_wr_as_1</td>
<td class="rt">1</td>
<td class="rt">1</td>
</tr><tr class="s10">
<td>bit_12_wr_as_1</td>
<td class="rt">1</td>
<td class="rt">1</td>
</tr><tr class="s10">
<td>bit_11_wr_as_1</td>
<td class="rt">1</td>
<td class="rt">1</td>
</tr><tr class="s10">
<td>bit_10_wr_as_1</td>
<td class="rt">1</td>
<td class="rt">1</td>
</tr><tr class="s10">
<td>bit_9_wr_as_1</td>
<td class="rt">1</td>
<td class="rt">1</td>
</tr><tr class="s10">
<td>bit_8_wr_as_1</td>
<td class="rt">1</td>
<td class="rt">1</td>
</tr><tr class="s10">
<td>bit_7_wr_as_1</td>
<td class="rt">1</td>
<td class="rt">1</td>
</tr><tr class="s10">
<td>bit_6_wr_as_1</td>
<td class="rt">1</td>
<td class="rt">1</td>
</tr><tr class="s10">
<td>bit_5_wr_as_1</td>
<td class="rt">1</td>
<td class="rt">1</td>
</tr><tr class="s10">
<td>bit_4_wr_as_1</td>
<td class="rt">1</td>
<td class="rt">1</td>
</tr><tr class="s10">
<td>bit_3_wr_as_1</td>
<td class="rt">1</td>
<td class="rt">1</td>
</tr><tr class="s10">
<td>bit_2_wr_as_1</td>
<td class="rt">1</td>
<td class="rt">1</td>
</tr><tr class="s10">
<td>bit_1_wr_as_1</td>
<td class="rt">1</td>
<td class="rt">1</td>
</tr><tr class="s10">
<td>bit_0_wr_as_1</td>
<td class="rt">1</td>
<td class="rt">1</td>
</tr></table><br clear=all>
</div>
<div name='LOCK_bits'>
<br clear=all>
<a name="inst_tag_LOCK_bits.LOCK"></a><span class="repname" id="inst_tag_LOCK_bits.LOCK">Summary for Variable LOCK</span>
<br clear=all>
<br clear=all>
<table align=left>
<tr class="sortablehead">
<td class="alfsrt">CATEGORY</td><td>EXPECTED</td><td>UNCOVERED</td><td>COVERED</td><td>PERCENT</td></tr><tr class="s2">
<td>User Defined Bins</td>
<td class="rt">64</td>
<td class="rt">48</td>
<td class="rt">16</td>
<td class="rt">25.00 </td>
</tr></table><br clear=all>
<br clear=all>
<span class=repname>User Defined Bins for LOCK</span>
<br clear=all>
<br clear=all>
<span class=repname>Uncovered bins</span>
<br clear=all>
<table align=left class="sortable">
<tr class="sortablehead">
<td class="alfsrt">NAME</td><td>COUNT</td><td>AT LEAST</td><td>NUMBER</td></tr><tr class="s3">
<td>bit_15_rd_as_1</td>
<td class="rt">0</td>
<td class="rt">1</td>
<td class="rt">1</td>
</tr><tr class="s3">
<td>bit_15_rd_as_0</td>
<td class="rt">0</td>
<td class="rt">1</td>
<td class="rt">1</td>
</tr><tr class="s3">
<td>bit_15_wr_as_0</td>
<td class="rt">0</td>
<td class="rt">1</td>
<td class="rt">1</td>
</tr><tr class="s3">
<td>bit_14_rd_as_1</td>
<td class="rt">0</td>
<td class="rt">1</td>
<td class="rt">1</td>
</tr><tr class="s3">
<td>bit_14_rd_as_0</td>
<td class="rt">0</td>
<td class="rt">1</td>
<td class="rt">1</td>
</tr><tr class="s3">
<td>bit_14_wr_as_0</td>
<td class="rt">0</td>
<td class="rt">1</td>
<td class="rt">1</td>
</tr><tr class="s3">
<td>bit_13_rd_as_1</td>
<td class="rt">0</td>
<td class="rt">1</td>
<td class="rt">1</td>
</tr><tr class="s3">
<td>bit_13_rd_as_0</td>
<td class="rt">0</td>
<td class="rt">1</td>
<td class="rt">1</td>
</tr><tr class="s3">
<td>bit_13_wr_as_0</td>
<td class="rt">0</td>
<td class="rt">1</td>
<td class="rt">1</td>
</tr><tr class="s3">
<td>bit_12_rd_as_1</td>
<td class="rt">0</td>
<td class="rt">1</td>
<td class="rt">1</td>
</tr><tr class="s3">
<td>bit_12_rd_as_0</td>
<td class="rt">0</td>
<td class="rt">1</td>
<td class="rt">1</td>
</tr><tr class="s3">
<td>bit_12_wr_as_0</td>
<td class="rt">0</td>
<td class="rt">1</td>
<td class="rt">1</td>
</tr><tr class="s3">
<td>bit_11_rd_as_1</td>
<td class="rt">0</td>
<td class="rt">1</td>
<td class="rt">1</td>
</tr><tr class="s3">
<td>bit_11_rd_as_0</td>
<td class="rt">0</td>
<td class="rt">1</td>
<td class="rt">1</td>
</tr><tr class="s3">
<td>bit_11_wr_as_0</td>
<td class="rt">0</td>
<td class="rt">1</td>
<td class="rt">1</td>
</tr><tr class="s3">
<td>bit_10_rd_as_1</td>
<td class="rt">0</td>
<td class="rt">1</td>
<td class="rt">1</td>
</tr><tr class="s3">
<td>bit_10_rd_as_0</td>
<td class="rt">0</td>
<td class="rt">1</td>
<td class="rt">1</td>
</tr><tr class="s3">
<td>bit_10_wr_as_0</td>
<td class="rt">0</td>
<td class="rt">1</td>
<td class="rt">1</td>
</tr><tr class="s3">
<td>bit_9_rd_as_1</td>
<td class="rt">0</td>
<td class="rt">1</td>
<td class="rt">1</td>
</tr><tr class="s3">
<td>bit_9_rd_as_0</td>
<td class="rt">0</td>
<td class="rt">1</td>
<td class="rt">1</td>
</tr><tr class="s3">
<td>bit_9_wr_as_0</td>
<td class="rt">0</td>
<td class="rt">1</td>
<td class="rt">1</td>
</tr><tr class="s3">
<td>bit_8_rd_as_1</td>
<td class="rt">0</td>
<td class="rt">1</td>
<td class="rt">1</td>
</tr><tr class="s3">
<td>bit_8_rd_as_0</td>
<td class="rt">0</td>
<td class="rt">1</td>
<td class="rt">1</td>
</tr><tr class="s3">
<td>bit_8_wr_as_0</td>
<td class="rt">0</td>
<td class="rt">1</td>
<td class="rt">1</td>
</tr><tr class="s3">
<td>bit_7_rd_as_1</td>
<td class="rt">0</td>
<td class="rt">1</td>
<td class="rt">1</td>
</tr><tr class="s3">
<td>bit_7_rd_as_0</td>
<td class="rt">0</td>
<td class="rt">1</td>
<td class="rt">1</td>
</tr><tr class="s3">
<td>bit_7_wr_as_0</td>
<td class="rt">0</td>
<td class="rt">1</td>
<td class="rt">1</td>
</tr><tr class="s3">
<td>bit_6_rd_as_1</td>
<td class="rt">0</td>
<td class="rt">1</td>
<td class="rt">1</td>
</tr><tr class="s3">
<td>bit_6_rd_as_0</td>
<td class="rt">0</td>
<td class="rt">1</td>
<td class="rt">1</td>
</tr><tr class="s3">
<td>bit_6_wr_as_0</td>
<td class="rt">0</td>
<td class="rt">1</td>
<td class="rt">1</td>
</tr><tr class="s3">
<td>bit_5_rd_as_1</td>
<td class="rt">0</td>
<td class="rt">1</td>
<td class="rt">1</td>
</tr><tr class="s3">
<td>bit_5_rd_as_0</td>
<td class="rt">0</td>
<td class="rt">1</td>
<td class="rt">1</td>
</tr><tr class="s3">
<td>bit_5_wr_as_0</td>
<td class="rt">0</td>
<td class="rt">1</td>
<td class="rt">1</td>
</tr><tr class="s3">
<td>bit_4_rd_as_1</td>
<td class="rt">0</td>
<td class="rt">1</td>
<td class="rt">1</td>
</tr><tr class="s3">
<td>bit_4_rd_as_0</td>
<td class="rt">0</td>
<td class="rt">1</td>
<td class="rt">1</td>
</tr><tr class="s3">
<td>bit_4_wr_as_0</td>
<td class="rt">0</td>
<td class="rt">1</td>
<td class="rt">1</td>
</tr><tr class="s3">
<td>bit_3_rd_as_1</td>
<td class="rt">0</td>
<td class="rt">1</td>
<td class="rt">1</td>
</tr><tr class="s3">
<td>bit_3_rd_as_0</td>
<td class="rt">0</td>
<td class="rt">1</td>
<td class="rt">1</td>
</tr><tr class="s3">
<td>bit_3_wr_as_0</td>
<td class="rt">0</td>
<td class="rt">1</td>
<td class="rt">1</td>
</tr><tr class="s3">
<td>bit_2_rd_as_1</td>
<td class="rt">0</td>
<td class="rt">1</td>
<td class="rt">1</td>
</tr><tr class="s3">
<td>bit_2_rd_as_0</td>
<td class="rt">0</td>
<td class="rt">1</td>
<td class="rt">1</td>
</tr><tr class="s3">
<td>bit_2_wr_as_0</td>
<td class="rt">0</td>
<td class="rt">1</td>
<td class="rt">1</td>
</tr><tr class="s3">
<td>bit_1_rd_as_1</td>
<td class="rt">0</td>
<td class="rt">1</td>
<td class="rt">1</td>
</tr><tr class="s3">
<td>bit_1_rd_as_0</td>
<td class="rt">0</td>
<td class="rt">1</td>
<td class="rt">1</td>
</tr><tr class="s3">
<td>bit_1_wr_as_0</td>
<td class="rt">0</td>
<td class="rt">1</td>
<td class="rt">1</td>
</tr><tr class="s3">
<td>bit_0_rd_as_1</td>
<td class="rt">0</td>
<td class="rt">1</td>
<td class="rt">1</td>
</tr><tr class="s3">
<td>bit_0_rd_as_0</td>
<td class="rt">0</td>
<td class="rt">1</td>
<td class="rt">1</td>
</tr><tr class="s3">
<td>bit_0_wr_as_0</td>
<td class="rt">0</td>
<td class="rt">1</td>
<td class="rt">1</td>
</tr></table><br clear=all>
<br clear=all>
<span class=repname>Covered bins</span>
<br clear=all>
<table align=left class="sortable">
<tr class="sortablehead">
<td class="alfsrt">NAME</td><td>COUNT</td><td>AT LEAST</td></tr><tr class="s10">
<td>bit_15_wr_as_1</td>
<td class="rt">1</td>
<td class="rt">1</td>
</tr><tr class="s10">
<td>bit_14_wr_as_1</td>
<td class="rt">1</td>
<td class="rt">1</td>
</tr><tr class="s10">
<td>bit_13_wr_as_1</td>
<td class="rt">1</td>
<td class="rt">1</td>
</tr><tr class="s10">
<td>bit_12_wr_as_1</td>
<td class="rt">1</td>
<td class="rt">1</td>
</tr><tr class="s10">
<td>bit_11_wr_as_1</td>
<td class="rt">1</td>
<td class="rt">1</td>
</tr><tr class="s10">
<td>bit_10_wr_as_1</td>
<td class="rt">1</td>
<td class="rt">1</td>
</tr><tr class="s10">
<td>bit_9_wr_as_1</td>
<td class="rt">1</td>
<td class="rt">1</td>
</tr><tr class="s10">
<td>bit_8_wr_as_1</td>
<td class="rt">1</td>
<td class="rt">1</td>
</tr><tr class="s10">
<td>bit_7_wr_as_1</td>
<td class="rt">1</td>
<td class="rt">1</td>
</tr><tr class="s10">
<td>bit_6_wr_as_1</td>
<td class="rt">1</td>
<td class="rt">1</td>
</tr><tr class="s10">
<td>bit_5_wr_as_1</td>
<td class="rt">1</td>
<td class="rt">1</td>
</tr><tr class="s10">
<td>bit_4_wr_as_1</td>
<td class="rt">1</td>
<td class="rt">1</td>
</tr><tr class="s10">
<td>bit_3_wr_as_1</td>
<td class="rt">1</td>
<td class="rt">1</td>
</tr><tr class="s10">
<td>bit_2_wr_as_1</td>
<td class="rt">1</td>
<td class="rt">1</td>
</tr><tr class="s10">
<td>bit_1_wr_as_1</td>
<td class="rt">1</td>
<td class="rt">1</td>
</tr><tr class="s10">
<td>bit_0_wr_as_1</td>
<td class="rt">1</td>
<td class="rt">1</td>
</tr></table><br clear=all>
</div>
</div>
<div class="ui-layout-center-inner-north">
<div id="center-bread-crumb" class="breadCrumb module urg-margin-bottom">
  <ul name="LOCK_bits">
    <li>
      <a href="#inst_tag_LOCK_bits.LOCK">Variable : LOCK</a>    </li>
  </ul>
  <ul name="router_stimulus_pkg::ral_reg_LOCK::cg_bits">
    <li>
      <a href="#inst_tag_router_stimulus_pkg::ral_reg_LOCK::cg_bits.LOCK">Variable : LOCK</a>    </li>
  </ul>
</div>
</div>
</div>
<div class="ui-layout-south">
<table align=center><tr><td class="s0 cl">0%</td>
<td class="s1 cl">10%</td>
<td class="s2 cl">20%</td>
<td class="s3 cl">30%</td>
<td class="s4 cl">40%</td>
<td class="s5 cl">50%</td>
<td class="s6 cl">60%</td>
<td class="s7 cl">70%</td>
<td class="s8 cl">80%</td>
<td class="s9 cl">90%</td>
<td class="s10 cl">100%</td></tr></table></div>
</body>
</html>
